The invention relates to a high speed complementary bipolar/CMOS process that provides a doping profile in the collectors of NPN transistors formed in an epitaxial layer so as to avoid a xe2x80x9cdipxe2x80x9d in N type dopant concentration, which dip causes slow speed and other undesirable properties of the NPN transistors.
Those skilled in the art know that it is difficult to provide a process for manufacturing an epitaxial silicon layer that is satisfactory for use in a high speed complementary bipolar/CMOS process. In such a process a very thin, lightly doped N type epitaxial silicon layer must be grown on a silicon wafer including both pre-formed P+ boron doped buried layers and N+ arsenic doped buried layers formed in a Pxe2x88x92 substrate. In a typical prior art complementary bipolar/CMOS process the epitaxial layer is doped lightly in situ with arsenic to a concentration of approximately 2xc3x971015 cmxe2x88x923 to achieve an optimal combination of characteristics of NPN, PNP and CMOS transistors to be formed. After the epitaxial deposition, the collector regions of the PNP and NPN transistors and the CMOS xe2x80x9cwellsxe2x80x9d are further doped by a combination of low energy and high energy boron or phosphorous implants, with energies and doses tailored to the needs of various xe2x80x9cfamiliesxe2x80x9d of devices. During conventional epitaxial growth and subsequent conventional thermal processing, both the P type buried layers and the N type buried layers up diffuse into the epitaxial layer. That reduces the thickness of the useful portions of the collector regions for the transistors being fabricated. Since the P+ and N+ buried layers diffuse at significantly different rates, the PNP transistors end up having shallower collectors than the NPN transistor.
Since the diffusion of a P+ buried layer accelerates more rapidly than an N+ layer with respect to temperature, differences in the thicknesses of the collectors of the PNP transistors and the NPN transistors can be minimized by keeping the xe2x80x9cDtxe2x80x9d of all high temperature process steps as low as possible. (xe2x80x9cDtxe2x80x9d is a term referring to the cumulative amount of time that the wafer is subjected to high temperatures, usually exceeding 1000xc2x0 C., after the epitaxial layer has been deposited.) The deep double implants used to form the collectors of the required depth for the NPN and PNP transistors, respectively, eliminate the need for high Dt diffusions after the formation of the epitaxial layer.
Note that a drawback associated with the large differential dopant diffusivity of arsenic buried layers and boron buried layers remains even for xe2x80x9clow Dt processingxe2x80x9d. For very low Dt processes, achieving the desirable PNP collector often results in producing an undesirable lightly doped N type subregion where an NPN collector region meets the N+ buried layer.
Furthermore, the value of Nxe2x88x92 dopant in the epitaxial layer must be selected to achieve the best characteristics of both the PNP and NPN transistors. If the Nxe2x88x92 concentration is as high as would be desirable for the NPN collector regions, then it would be far too high for the collectors of the PNP transistors. Therefore, a lower N-epitaxial dopant level, indicated by numeral 14 in FIG. 2, is selected instead. Then an N type ion implantation is applied to the surface, raising the N type dopant concentration to a suitable level for the NPN collectors. Unfortunately, it is impractical to provide the dose and energies needed to produce the xe2x80x9cflatxe2x80x9d N type epitaxial dopant concentration profile at the bottoms of the NPN collector regions. Consequently, the failure of the implanted ions to reach the bottoms of the NPN collector regions is a partial cause of the xe2x80x9cdipxe2x80x9d 20 in FIG. 2.
The problem of such light doping is further aggravated by boron autodoping, wherein a large number of P type boron atoms escape from the large P+ buried layer area and then diffuse into the surface of the Pxe2x88x92 substrate and into the lightly doped N type epitaxial layer being grown, reducing or xe2x80x9ccompensatingxe2x80x9d its dopant concentration. This results in increased collector resistance and corresponding increased VCE(sat) voltage, reduced fT (i.e., the unity gain frequency or cutoff frequency), lower NPN switching speeds, and higher power dissipation.
FIGS. 1 and 2 show typical dopant concentration profiles for the PNP and NPN collector regions, respectively, made by a conventional complementary bipolar process after completion of a field oxidation step, during which most of the dopant diffusion occurs.
The dopant profiles of FIGS. 1 and 2 were obtained from a simulation of the dopant diffusions for the conventional epitaxial deposition process. The process simulation was calibrated to match experimental results measured from a substrate with a large percentage (for example 80%) of the wafer surface area implanted with a dose of approximately 1xc3x971015 cmxe2x88x922 of boron followed by a P+ buried layer diffusion. (As those skilled in the art will recognize, the reason the large percentage of the P+ wafer substrate area has P+ xe2x80x9cburied layer materialxe2x80x9d therein is to reduce substrate resistance and increase latch-up immunity of bipolar transistors and CMOS transistors.)
The prior art epitaxial process referred to above includes a high temperature H2 pre-bake followed by a high temperature purge and then by a 1.5 micron deposition of an epitaxial layer of lightly arsenic (N type) doped single crystal silicon. The large amount of P+ surface area of the substrate causes a large amount of boron auto-doping into the lightly doped N type epitaxial layer being formed. The amount of corresponding boron (PF) autodoping in the dopant concentration profile of prior art FIGS. 1 and 2 was computed using simulated TSUPREM-4 profiles, and the simulated profiles were calibrated to match the measured experimental results. The TSUPREM-4 simulation program is a commercially available software package xe2x80x9cTwo-dimensional Process Simulation Programxe2x80x9d, sold by Avant! Corporation, formerly Technology Modeling Associates.
For thin epitaxial layers (e.g., less than two microns in thickness), the autodoping strongly influences the transistor collector dopant concentration profiles. The large P+ substrate surface area mentioned above contributes a significant amount of boron autodoping during the epitaxial growth, which aggravates the above-mentioned problems with the performance of the NPN transistors, further reduces the depth of the PNP collector regions, and increases the difference between the breakdown characteristics of NPN and PNP transistors. The standard flat dopant profile epitaxial process techniques used to generate the profiles in prior art FIGS. 1 and 2 are not able to correct these problems.
Referring to FIGS. 1 and 2, the dopant concentration profiles of the prior art NPN and PNP collector regions are noticeably different when a standard epitaxial process is used. The differences between the peak implant concentration depths (commonly referred to as Rp) for phosphorus and boron implants is another cause of the large difference in the dopant concentration profiles of the NPN and PNP collector regions when practical implant energies are used. This difference is further aggravated by the boron autodoping. The NPN collector region, doped by a combination of low and high energy implants, shows a significant dopant concentration dip at its bottom, indicated by reference arrows 20 in FIG. 1. This very lightly doped region adversely affects both the AC and DC performance of the NPN transistor by raising its collector region resistivity. This increases its collector resistance and thereby reduces fT and increases the collector-to-emitter saturation voltages of the NPN transistor.
Prior experimentation in forming arsenic doped N+ epitaxial caps in the hope of increasing the doping concentration at the bottoms of the NPN collector regions has failed to adequately compensate for the boron autodoping at the epitaxial/substrate interface.
Thus, there is a need for an improved epitaxial process for complementary bipolar/CMOS for providing bipolar transistors, especially NPN transistors, with more ideal collector profiles leading to lower collector resistances and higher values of fT than has been previously achievable.
Accordingly, it is an object of the invention to provide a high speed complementary bipolar/CMOS epitaxial process that provides NPN transistors in which undesirable effects of a dip or decrease in the N type collector dopant concentration profile close to an N+ buried layer are avoided.
It is another object of the invention to provide a high speed complementary bipolar/CMOS epitaxial process in which the NPN and PNP transistors have similar performance characteristics.
It is another object of the invention to provide a high speed complementary bipolar/CMOS process in which the NPN transistors have higher fT, lower collector resistance, and lower collector-to-emitter saturation voltage than has been previously achievable.
It is another object of the invention to provide a high speed complementary bipolar/CMOS process with a very uniform collector dopant concentration profile which leads to a high cutoff frequency fT that is higher than previously has been achieved.
It is another object of the invention to provide a high speed complementary bipolar/CMOS process wherein process techniques that allow eliminating an undesirable dip in the dopant concentration profile of the collectors of the NPN transistors also allow optimization of the dopant concentration profile of the collectors of the PNP transistors.
Briefly described, and in accordance with one embodiment thereof, the invention provides a method of making an epitaxial layer on a P type silicon substrate having a P+ field layer region in most of a major surface of the substrate. The method includes loading the substrate in a reactor with a carrier gas therein, pre-baking the substrate, further heating the substrate, providing N+ dopant gas with the carrier gas, deoxidizing the substrate in the presence of the N+ dopant gas, depositing a first intrinsic epitaxial cap layer, performing a first bake cycle, depositing a second intrinsic epitaxial cap layer, performing a second bake cycle, and depositing an Nxe2x88x92 epitaxial layer having a thickness substantially greater than the thickness of either of the first and second cap layers. The process avoids an undesirable dip in the dopant concentration profile of the collector of PNP transistors formed in the epitaxial layer and results in higher fT, lower VSAT devices.